The present invention relates generally to the manufacture of high speed MOS semiconductor devices fabricated on strained lattice semiconductor substrates, and devices obtained thereby. Specifically, the present invention relates to an improved method of performing thermal annealing of amorphized and dopant-implanted regions of strained lattice semiconductor layers for effecting epitaxial re-crystallization thereof and dopant activation, without incurring significant stress relaxation of the strained lattice.
Recently, there has been much interest in various approaches with the aim or goal of developing new semiconductor materials which provide increased speeds of electron and hole flow therethrough, thereby permitting fabrication of semiconductor devices, such as integrated circuit (IC) devices with higher operating speeds, enhanced performance characteristics, and lower power consumption. One such material which shows promise in attaining the goal of higher device operating speeds is termed xe2x80x9cstrained siliconxe2x80x9d.
According to this approach, a very thin, tensilely strained, crystalline silicon (Si) layer is grown on a relaxed, graded composition Sixe2x80x94Ge buffer layer several microns thick, which Sixe2x80x94Ge buffer layer in turn is formed on a suitable crystalline substrate, e.g., a Si wafer or a silicon-on-insulator (SOI) wafer. Strained Si technology is based upon the tendency of the Si atoms, when deposited on the Sixe2x80x94Ge buffer layer, to align with the greater lattice constant (spacing) of the Si and Ge atoms therein (relative to pure Si). As a consequence of the Si atoms being deposited on a substrate (Sixe2x80x94Ge) comprised of atoms which are spaced further apart, they xe2x80x9cstretchxe2x80x9d to align with the underlying Si and Ge atoms, thereby xe2x80x9cstretchingxe2x80x9d or tensilely straining the deposited Si layer. Electrons and holes in such strained Si layers have greater mobility than in conventional, relaxed Si layers with smaller inter-atom spacings, i.e., there is less resistance to electron and/or hole flow. For example, electron flow in strained Si may be up to about 70% faster compared to electron flow in conventional Si. Transistors and IC devices formed with such strained Si layers can exhibit operating speeds up to about 35% faster than those of equivalent devices formed with conventional Si, without necessity for reduction in transistor size.
However, an important concern in the manufacture of practical semiconductor devices utilizing strained semiconductor layers, e.g., strained Si layers, is the requirement for maintaining the tensilely strained condition of the strained semiconductor layer throughout device processing, without incurring significant strain relaxation disadvantageously leading to reduction in electron/hole mobility resulting in degradation in device performance characteristics. For example, many device fabrication steps, including for example, annealing for re-crystallization of amorphized regions and activation of implanted dopant species, frequently involve high temperature processing at temperatures on the order of about 900-1,100xc2x0 C. for intervals sufficient to result in significant relaxation in the tensile strain of the Si layer, which in turn results in a lowering of the electron and hole mobilities therein to values comparable to those of conventional Si layers, whereby the potential advantages attributable to enhanced electron/hole mobility in the strained Si layer are partially or wholly lost.
Accordingly, there exists a need for improved methodology for fabrication of semiconductor devices with strained semiconductor layers, notably strained Si layers, which substantially eliminates, or at least minimizes, deleterious stress relaxation during device processing at elevated temperatures, e.g., as in thermal annealing processing for re-crystallization and dopant activation of amorphized, dopant-implanted source and drain regions forming part of MOS-type transistors and CMOS devices.
The present invention, wherein thermal annealing processing for re-crystallization and dopant activation of amorphized, dopant-implanted source and drain regions forming part of MOS-type transistors and CMOS devices is performed at a minimum temperature sufficient to cause epitaxial re-crystallization of amorphous, dopant-implanted region in a strained lattice semiconductor layer to re-form an epitaxial, strained lattice semiconductor layer having substantially the original amount of lattice strain, effectively eliminates, or at least minimizes, disadvantageous strain relaxation of the strained lattice semiconductor arising from the thermal annealing. As a consequence, the inventive methodology facilitates manufacture of high speed, high performance, reduced power consumption semiconductor devices utilizing strained semiconductor technology. Further the methodology afforded by the present invention enjoys diverse utility in the manufacture of numerous and various semiconductor devices and/or components therefor which require use of strained semiconductor technology for enhancement of device speed and lower power consumption.
An advantage of the present invention is an improved method for manufacturing a semiconductor device comprising a strained lattice semiconductor layer.
Another advantage of the present invention is an improved method for manufacturing a semiconductor device comprising epitaxial re-crystallization of an amorphous, dopant-implanted region of a strained lattice semiconductor layer without incurring significant stress relaxation.
Yet another advantage of the present invention is an improved method for manufacturing high-speed MOS-type semiconductor devices comprising strained lattice semiconductor layers.
Still another advantage of the present invention is improved, high-speed MOS-type semiconductor devices fabricated on or within substrates including strained lattice semiconductor layers.
Additional advantages and other aspects and features of the present invention will be set forth in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the invention, the foregoing and other advantages are obtained in part by a method of manufacturing a semiconductor device, comprising the steps of:
(a) providing a semiconductor substrate comprising a strained lattice semiconductor layer at an upper surface thereof, the strained lattice semiconductor layer having a pre-selected amount of lattice strain therein;
(b) forming a device structure in the semiconductor substrate by a process comprising forming at least one amorphous region in at least one portion of the strained lattice semiconductor layer; and
(c) thermal annealing the device structure at a minimum temperature sufficient to effect epitaxial re-crystallization of the at least one amorphous region in the strained lattice semiconductor layer to re-form a strained lattice semiconductor layer having substantially the pre-selected amount of lattice strain, whereby strain relaxation of the strained lattice semiconductor arising from the thermal annealing is substantially eliminated or minimized.
According to embodiments of the present invention, step (b) further comprises implanting a dopant species in the at least one amorphous region; and
step (c) further comprises simultaneously epitaxial re-crystallizing the at least one amorphous region in the strained lattice semiconductor layer and activating the implanted dopant species therein.
In accordance with further embodiments of the present invention:
step (a) comprises providing a semiconductor substrate comprising a crystalline semiconductor layer below the strained lattice semiconductor layer;
step (b) still further comprises forming at least one amorphous region in at least one portion of the crystalline semiconductor layer and implanting a dopant species therein; and
step (c) still further comprises simultaneously epitaxial re-crystallizing the at least one amorphous region in the strained lattice semiconductor layer and activating the implanted dopant species therein, and re-crystallizing the at least one amorphous region in the at least one portion of the crystalline semiconductor layer and activating the implanted dopant species therein.
According to certain embodiments of the present invention, step (c) comprises performing laser thermal annealing (LTA) or rapid thermal annealing (RTA).
Embodiments of the invention include, as step (b), forming a PMOS transistor, an NMOS transistor, or a CMOS device, wherein:
step (a) comprises providing a semiconductor substrate including a crystalline, graded composition silicon-germanium (Sixe2x80x94Ge) layer, with a lattice-matched crystalline silicon (Si) layer on a first side of the Sixe2x80x94Ge layer and comprising the strained lattice semiconductor layer.
According to further embodiments of the present invention:
step (a) comprises providing a semiconductor substrate which further includes a crystalline silicon layer on a second, opposite side of the Sixe2x80x94Ge layer;
step (b) comprises sequential steps of:
i. forming at least one gate oxide layer/gate electrode stack on at least one surface portion of the Si strained lattice semiconductor layer;
ii. performing a pre-amorphization implantation of the Si strained lattice semiconductor layer utilizing the at least one gate oxide layer/gate electrode layer stack as an implantation mask, to form at least one pair of amorphous regions in the Si strained lattice semiconductor layer aligned with opposite side edges of the gate oxide layer/gate electrode layer stack; and
iii. implanting dopant species of one conductivity type in the at least one pair of amorphous regions in the Si strained lattice semiconductor layer utilizing the gate oxide layer/gate electrode layer stack as an implantation mask; and
step (c) comprises thermal annealing the device structure to simultaneously re-crystallize the at least one pair of amorphous regions in the Si strained lattice semiconductor layer and activate the implanted dopant species therein.
In accordance with embodiments of the present invention:
step (a) comprises providing a semiconductor substrate with a Si strained lattice semiconductor layer having a pre-selected thickness; and
steps (b) and (c) together form at least one pair of source/drain extension regions vertically aligned with side edges of the gate oxide layer/gate electrode layer stack and extending in the Si strained lattice semiconductor layer to a depth above and proximate an interface between the Si strained lattice semiconductor layer and the graded composition Sixe2x80x94Ge layer.
According to further embodiments of the present invention:
step (b) further comprises sequential steps of:
iv. forming sidewall spacers on opposite side edge surfaces of the at least one gate oxide layer/gate electrode layer stack;
v. performing a post-amorphization implantation of the Sixe2x80x94Ge layer utilizing the at least one gate oxide layer/gate electrode layer stack with the sidewall spacers thereon as an implantation mask, to form at least one pair of amorphous regions in the Sixe2x80x94Ge layer; and
vi. implanting dopant species of the one conductivity type in the at least one pair of amorphous regions in the Sixe2x80x94Ge layer utilizing the at least one gate oxide layer/gate electrode layer stack with the sidewall spacers thereon as an implantation mask; and
step (c) further comprises thermal annealing the device structure to simultaneously epitaxial re-crystallize the at least one pair of amorphous regions in the Si strained lattice semiconductor layer and activate the implanted dopant species therein, and to re-crystallize the at least one pair of amorphous regions in the Sixe2x80x94Ge layer and activate the implanted dopant species therein.
In accordance with certain embodiments of the present invention:
steps (b) and (c) together further form at least one pair of source/drain regions vertically aligned with the sidewall spacers on the side edges of the gate oxide layer/gate electrode layer stack and extending to a pre-selected depth in the Sixe2x80x94Ge layer.
Embodiments of the present invention include performing step (c) by laser thermal annealing (LTA) or rapid thermal annealing (RTA) at a temperature from about 500 to about 600xc2x0 C. for from about 30 sec. to about 5 hrs. to simultaneously re-crystallize and activate implanted dopant species in each of the amorphous regions in the Si strained lattice semiconductor layer and the Sixe2x80x94Ge layer.
Another aspect of the present invention is a semiconductor device comprising a semiconductor substrate including a crystalline, strained lattice semiconductor layer at an upper surface thereof, the strained lattice semiconductor layer including at least one epitaxial recrystallized region formed by a thermal annealing process conducted at a minimum temperature sufficient to effect epitaxial re-crystallization of at least one amorphous region therein to re-form a crystalline, strained lattice semiconductor layer without incurring strain relaxation of the strained lattice semiconductor arising from the thermal annealing.
According to embodiments of the present invention, the at least one recrystallized region further comprises a dopant therein, and the semiconductor device comprises at least one MOS device which includes one or more of a PMOS transistor, an NMOS transistor, and a CMOS device.
In accordance with certain embodiments of the present invention, the semiconductor substrate includes a crystalline, graded composition silicon-germanium (Sixe2x80x94Ge) layer, with a lattice-matched crystalline silicon (Si) layer on a first side of the Sixe2x80x94Ge layer and comprising the strained lattice semiconductor layer, and a crystalline silicon layer on a second, opposite side of the Sixe2x80x94Ge layer.
According to embodiments of the present invention, the semiconductor device is formed according to a process comprising sequential steps of:
(a) forming at least one gate oxide layer/gate electrode stack on at least one surface portion of the Si strained lattice semiconductor layer, the Si strained semiconductor layer having a pre-selected amount of lattice strain therein;
(b) performing a pre-amorphization implantation of the Si strained lattice semiconductor layer utilizing the at least one gate oxide layer/gate electrode layer stack as an implantation mask, to form at least one pair of amorphous regions in the Si strained lattice semiconductor layer aligned with opposite side edges of the gate oxide layer/gate electrode layer stack; and
(c) implanting dopant species of one conductivity type in the at least one pair of amorphous regions in the Si strained lattice semiconductor layer utilizing the gate oxide layer/gate electrode layer stack as an implantation mask; and
(d) thermal annealing to simultaneously re-crystallize the at least one pair of amorphous regions in the Si strained lattice semiconductor layer and activate the implanted dopant species therein, the thermal annealing performed at a minimum temperature sufficient to effect epitaxial re-crystallization of the at least one pair of amorphous regions in the strained lattice semiconductor layer to re-form a strained lattice semiconductor layer having substantially the pre-selected amount of lattice strain, whereby strain relaxation of the strained lattice semiconductor arising from the thermal annealing is substantially eliminated or minimized; wherein:
steps (b)-(d) form at least one pair of source/drain extension regions vertically aligned with side edges of the gate oxide layer/gate electrode layer stack and extending in the Si strained lattice semiconductor layer to a depth above and proximate an interface between the Si strained lattice semiconductor layer and the graded composition Sixe2x80x94Ge layer.
In accordance with further embodiments of the present invention, the semiconductor device is formed according to a process which further comprises sequential steps of:
(e) forming sidewall spacers on opposite side edge surfaces of the at least one gate oxide layer/gate electrode layer stack after step (c) and before step (d);
(f) performing a post-amorphization implantation of the Sixe2x80x94Ge layer utilizing the at least one gate oxide layer/gate electrode layer stack with the sidewall spacers thereon as an implantation mask, to form at least one pair of amorphous regions in the Sixe2x80x94Ge layer; and
(g) implanting dopant species of the one conductivity type in the at least one pair of amorphous regions in the Sixe2x80x94Ge layer, utilizing the at least one gate oxide layer/gate electrode layer stack with the sidewall spacers thereon as an implantation mask; wherein:
step (d) further comprises thermal annealing to simultaneously epitaxial re-crystallize the at least one pair of amorphous regions in the Si strained lattice semiconductor layer and activate the inplanted dopant species therein, and to re-crystallize the at least one pair of amorphous regions in the Sixe2x80x94Ge layer and activate the implanted dopant species therein; and
steps (d)-(g) form at least one pair of source/drain regions vertically aligned with the sidewall spacers on the side edges of the gate oxide layer/gate electrode layer stack and extending to a pre-selected depth in the Sixe2x80x94Ge layer.
According to certain embodiments of the present invention, step (c) comprises performing laser thermal annealing (LTA) or rapid thermal annealing (RTA) at a temperature from about 500 to about 600xc2x0 C. for from about 30 sec. to about 5 hrs. to simultaneously re-crystallize and activate implanted dopant species in each of the amorphous regions in the Si strained lattice semiconductor layer and the Sixe2x80x94Ge layer.